1. Field of the Invention
The invention relates generally to a chip scale package and a manufacturing method therefor. More particularly, the invention provides a chip scale package that is constructed from a leadframe carrier.
2. Description of the Related Art
Chip scale package technology is increasingly developed to further miniaturize electronic devices with higher density. A chip scale package is usually defined as a packaging structure the length of which is below 1.2 times that of the packaged chip or, alternatively, as a packaging structure that has a chip to package surface area ratio greater than 80%. Surface mount technology (SMT) is conventionally used to electrically connect the chip scale package on a printed circuit board. The most common chip scale packages include bump chip carrier (BCC) packages, quad flat nonleaded (QFN) packages, and leadframe type packages.
FIG. 1 is a schematic view that illustrates a conventional BCC package. As illustrated, a BCC package known in the prior art comprises a chip 100, an adhesive layer 104, a plurality of conductive wires 106, a plurality of terminals 108, and an encapsulating body 110. The chip 100 is attached on the adhesive layer 104, and has a plurality of bonding pads 102 that are electrically connected to the terminals 108 via the conductive wires 106. The encapsulating body 110 covers the chip 100 and the conductive wires 106, while exposing a lower surface of the adhesive layer 104 to promote heat dissipation. The terminals 108 are externally exposed to allow electrical connection of the package on a circuit board via SMT (not shown). To expose the adhesive layer 104 through the encapsulating body 110 and form the terminals 108, etching is usually required, which may complicate the manufacturing process.
FIG. 2 is a schematic view that illustrates a QFN package known in the prior art. As illustrated, a QFN package of the prior art is constructed from a leadframe 208 that comprises a die pad 208a and a plurality of leads 208b. A chip 200, having an active surface provided with a plurality of bonding pads 202, is attached on the die pad 208a via an adhesive layer 204, and is electrically connected via conductive wires 206. Some of the bonding pads 202 are electrically connected to the leads 208b via conductive wires 206b, while other bonding pads 202 are grounded by electrically connecting the die pad 208a via conductive wires 206a. An encapsulating body 210 covers the chip 200, the adhesive layer 204, and the conductive wires 206a, 206b, while exposing a lower surface of the die pad 208a and a portion of the leads 208b to respectively dissipate heat and achieve the external electrical connection.
FIG. 3 is a schematic view that illustrates a leadframe type package known in the prior art. As illustrated, a known leadframe type package is constructed from a carrier leadframe 308 that comprises a die pad 308a and a plurality of leads 308b. A chip 300, having an active surface provided with a plurality of bonding pads 302, is attached on the die pad 308a via an adhesive layer 304. The bonding pads 302 are electrically connected to the leads 308b via conductive wires 306. An encapsulating body 310 respectively covers the chip 300, the adhesive layer 304, the conductive wires 306, the die pad 308a, and partially the leads 308b. A portion of the leads 308a is externally exposed for external electrical connections. Heat dissipation in this type of package is typically performed via the leads or an additional heat sink, which may be insufficient with respect to the amount of heat irradiated from the packaged chip.
Furthermore, all of the aforementioned packages use bonding or conductive wires to establish the electrical connection of the chip within the package, which limits the dimensional reduction of the package. Compared to flip chip connection, wire bonding connection further has a longer signal path, which produces undesirable parasitic inductance effects. To achieve flip chip connection, the chip usually needs undergo an additional redistribution step. This redistribution rearranges the positions of the bonding pads, usually laid peripherally around the chip in wire bonding connection, in an area array distribution with larger pitches between the bonding pads. Unfortunately, this bonding pad redistribution increases the circuit length, which also causes parasitic inductance effects.